Lead/lag compensation

In the previous section, we learned what desirable closed-loop performance looks like and how to change the loop gain $L(s) = C(s)G(s)$ to achieve it. We also looked at how the familiar PID family can serve this purpose. In this section, we look at a new type of compensator called lead/lag, which gives us additional flexibility compared to PID.

What is lead/lag compensation?¶

A “phase lead compensator” (or just “lead”) is a pole-zero pair where the zero occurs at a lower frequency than the pole. It is called a lead compensator because we will see that it adds a bump in phase lead. We can write this in many ways, for example:

Different forms are used depending on our desired low-frequency ($s\to 0$) or high-frequency ($s\to\infty$) gain. For example:

• The first has a low-frequency gain (DC gain) of 1 and a high-frequency gain of $\frac{\tau_1}{\tau_2}$.

• The second has a low-frequency gain of $\frac{b}{a}$ and a high-frequency gain of 1.

A “phase lag compensator” (or just “lag”) has the same form as Eq. (1), but with $\tau_1<\tau_2$ and $b>a$ instead. So now the pole occurs at a lower frequency than the zero. It is called a lag compensator because we will see that it adds a bump in phase lag.

Lead/lag compensators are used in two main ways:

1. As a replacement for PID control. They can achieve similar benefits but without some of the drawbacks discussed in the previous section.

2. As a fine-tuning step; to improve stability margins of an existing design.

Lead/lag as a PID alternative¶

Lag vs. PI¶

We can view a lag compensator as replacing the integrator with a low-frequency pole while keeping the same DC gain. In other words:

Both forms above have a high-frequency gain of $K$. Here is a Bode plot comparison:

Let’s compare the lag compensator to the PI compensator:

• 🟢 The phase lag is now more localized, so it only has an effect between $b$ and $a$ rather than for all frequencies below $a$. A smaller $b$ means less localization.

• 🔴 The Bode magnitude plot flattens out at $\omega < b$. So we do not have infinite gain at low frequencies and do not increase the system type (only an integrator can do that). However, the smaller we make $b$, the larger the low-frequency gain, so we can still substantially reduce steady-state error, even if we can’t make it zero.

In the limit $b\to 0$, the lag compensator becomes a PI compensator. In practice, lags offer flexibility when we don’t want to add a pure integrator but still want some of the benefits of doing so.

Lead vs. PD¶

We can view a lead compensator as adding an extra high-frequency pole to a PD compensator while keeping the same low-frequency gain. In other words:

Both forms above have a low-frequency gain of $K$. Here is a Bode plot comparison:

Let’s compare the lead compensator to the PD compensator:

• 🟢 The Bode magnitude plot flattens out at $\omega > a$. So we no longer reduce the high-frequency roll-off. However, we still increase the high-frequency gain, which will amplify noise at high frequencies. Larger $a$ means more amplification.

• 🔴 The phase lead is more localized, so it only has an effect between $b$ and $a$ rather than for all frequencies above $b$. A larger $a$ means less localization.

In the limit $a\to\infty$, the lead compensator becomes a PD compensator. In practice, leads are often used instead of PD control because they offer more flexibility. Moreover, it is impossible to implement a pure derivative anyway, so lead compensation is often the only choice!

Lead-lag vs. PID¶

A lead-lag compensator is just the product of a lead and a lag:

This combines lead and lag similar to how PID combined PI and PD. It is a very flexible form that can be used to achieve a wide variety of Bode plots. For example:

As $b_2\to 0$ and $a_1\to\infty$, the lead-lag compensator becomes a PID compensator.

Usually the gain crossover is designed to be near the lead pole/zero pair, so that the lead can improve phase margin. The lag pole/zero pair is designed to be at a much lower frequency, so that it can improve low-frequency gain without affecting phase margin. The lead and lag parts serve different purposes so they are often designed separately.

Lead/lag for fine-tuning¶

An other use for lead/lag compensation is to fine-tune an existing design. Suppose we have an open-loop plant $G(s)$, which already includes compensation to achieve satisfactory low-frequency tracking performance and high-frequency noise rejection. However, the stability margins are not good enough. Two obvious solutions are:

• Reducing the proportional gain (to reduce the gain crossover frequency, thereby increasing phase margin). Unfortunately, this also reduces our low-frequency gain and compromises our tracking and disturbance rejection. It also reduces bandwidth, which may be undesirable.

• Adding a zero, e.g. a PD controller (to add phase lead and thereby increase phase margin). Unfortunately, this also also reduces our high-frequency roll-off, which compromises noise rejection and robustness to unmodeled dynamics.

Lead and lag compensation can be used to improve stability margins of a given design without changing its low-frequency gain or high-frequency roll-off. The following analysis will be more quantitative, since we will develop guidelines for how to pick the parameters of the lead and lag compensators to achieve a desired phase margin improvement.

Lead compensation¶

We will use a slightly different parameterization of the lead compensator than the one we used for PD control:

This compensator has a zero at $s= -\frac{1}{\tau}$ and a pole at $s= -\frac{1}{\alpha \tau}$. Therefore, the zero is at a lower frequency than the pole, so the Bode plot has a “phase lead bump”:

Note that $\tau$ controls the location of the zero and $\alpha$ controls the space between the pole and zero. The zero is at $\frac{1}{\tau}$ and the smaller we pick $\alpha$, the farther the pole. For example, $\alpha=0.1$ makes the pole one decade larger than the zero.

The farther apart the pole and zero are (i.e., the smaller $\alpha$ is), the larger the phase lead bump, up to a maximum of 90°. There is a neat formula for calculating the phase lead bump as a function of $\alpha$:

Derivation of the phase lead bump formula

The bump occurs midway between the pole and zero. The frequency response of the lead compensator at this midpoint $\omega_m = \frac{1}{\sqrt{\alpha}\tau}$ is:

$$C_\textsf{lead}(j\omega_m) = \frac{j\frac{1}{\sqrt{\alpha}} + 1}{j\sqrt{\alpha} + 1}$$

(7)

The magnitude of this complex number is:

$$\left|\frac{j\frac{1}{\sqrt{\alpha}} + 1}{j\sqrt{\alpha} + 1}\right| = \sqrt{\frac{\frac{1}{\alpha} + 1}{\alpha + 1}} = \frac{1}{\sqrt{\alpha}}$$

(8)

Multiply by the conjugate to find the real and imaginary parts:

$$\begin{aligned} \frac{j\frac{1}{\sqrt{\alpha}} + 1}{j\sqrt{\alpha} + 1} &= \frac{(j\frac{1}{\sqrt{\alpha}} + 1)(1 - j\sqrt{\alpha})}{(j\sqrt{\alpha} + 1)(1 - j\sqrt{\alpha})} \\ &= \frac{2 + j\left(\frac{1}{\sqrt{\alpha}} - \sqrt{\alpha}\right)}{1 + \alpha} \\ &= \frac{2}{1+\alpha} + j\frac{\frac{1}{\sqrt{\alpha}} - \sqrt{\alpha}}{1+\alpha} \\ &= \frac{2}{1+\alpha} + j\frac{1-\alpha}{\sqrt{\alpha}(1+\alpha)} \end{aligned}$$

(9)

The phase of the frequency response $\phi$ therefore satisfies the following triangle, where we have put in the real part, imaginary part, and magnitude:

The sine of $\phi$ is the ratio of the imaginary part to the magnitude:

$$\sin \phi = \frac{\frac{1-\alpha}{\sqrt{\alpha}(1+\alpha)}}{\frac{1}{\sqrt{\alpha}}} = \frac{1-\alpha}{1+\alpha}$$

(10)

The alternative formula can be obtained by rearranging and solving for $\alpha$ in terms of $\sin\phi$.

We will see an example of lead compensation design at the end of this section.

Lag compensation¶

We will use a different parameterization of the lag compensator than the one we used for PI control. This time, we choose a DC gain of 1, so that it does not affect the low-frequency gain. This is in sharp contrast to using lag compensation as a replacement for PI control, where we used it to increase low-frequency gain.

The formula is the same as the lead compensator, but the parameter is larger than 1 instead of smaller than 1. This means that the pole is at a lower frequency than the zero, so the Bode plot has a “phase lag bump”:

The same formula from (6) applies, but with $\alpha$ replaced by $\beta$. This will lead to a negative $\phi$, as expected for a lag compensator.

However, the lag compensator is not used for its phase lag, as this can’t help us improve phase margin. Instead, it is used for the dip in gain it provides. The total drop in decibels (as a positive number) incurred by the lag compensator at high frequencies is given by:

We will see an example of lag compensation design at the end of this section.

Fine-tuning example¶

Consider the following open-loop plant^[1]

This plant already includes a PI controller we designed to achieve desirable tracking performance for the closed-loop system. Unfortunately, introducing the integrator has made our stability margins quite bad. Here is the Bode plot of $G(s)$:

The goal is to design a compensator that will give us a phase margin of at least 48° while preserving the frequency response at low-frequency (to maintain tracking performance) and keeping the same high-frequency roll-off (to maintain noise rejection).

We will solve this problem with both lead compensation and lag compensation and then compare the results.

Lead design¶

Our current phase margin is 18°. To increase our phase margin to 48°, we need to add 30° of phase lead. To be safe, we will use $\phi_{\textsf{des}} = 36\degree$ to give ourselves a buffer. Using Eq. (6), we can calculate $\alpha$:

The gain gain bump is $\frac{1}{\sqrt{\alpha}} \approx 2 \approx 6\text{ dB}$. The uncompensated magnitude plot drops to -6 dB at roughly 22 rad/s, so we will set $\omega_{cg}' = 22$ rad/s.

Next, we pick $\tau$ by putting the gain crossover frequency at $\omega_{cg}'$. Using Eq. (12), we obtain

Putting this together, our lead compensator is:

Here are Bode plots of our original loop $G(s)$ and our compensated loop $C_\textsf{lead}(s)G(s)$:

As we can see, we now have a nice phase margin of about 49° and the same low-frequency gain and high-frequency roll-off as before. The price we had to pay was a modest increase in bandwidth from 15 rad/s to about 19 rad/s, and a small high-frequency gain bump.

Different designs are possible by tweaking $\tau$ and $\alpha$, but this is a good starting point that achieves our design goals.

Lag design¶

If we want to achieve a phase margin of 48° by moving the gain crossover frequency to the left, we need to find the new gain crossover frequency $\omega_{cg}^\textsf{des}$ that corresponds to a phase margin of 48°. This is about 4 rad/s. At this frequency, the magnitude plot of $G(s)$ is about 20 dB. Therefore, we need to shift the high-frequency gain by -20 dB, or a gain of 0.1. Using Eq. (16), we can calculate $\beta$:

Next, we pick $\tau$ so that the phase lag bump occurs at a frequency that is much lower than our gain crossover and does not affect our phase margin. Using Eq. (17):

Therefore, $\tau \geq 2.5$. Let’s pick $\tau = 5$ to be safe. Together with, $\beta = 10$, our lag compensator is:

Here are Bode plots of our original loop $G(s)$ and our compensated loop $C_\textsf{lag}(s)G(s)$:

Once again, we have achieved a phase margin of about 49° and the same low-frequency gain and high-frequency roll-off as before. The price we had to pay this time was a decrease in bandwidth from 15 rad/s to about 4 rad/s. As a bonus, we also reduced our high-frequency gain by 20 dB, resulting in improved noise rejection and robustness to unmodeled dynamics.

Different designs are possible by tweaking $\tau$ and $\beta$, but this is a good starting point that achieves our design goals.

Comparison of designs¶

Both designs achieved the target phase margin of 48°. The difference is that the lead design increased the gain crossover, while the lag design decreased it. So the lead design increases bandwidth, leading to a more aggressive/sensitive controller, while the lag design decreases bandwidth, leading to a slower but more robust controller.

Returning to our familiar time-domain analysis, we can compare the closed-loop transfer functions of our original system, lead-compensated system, and lag-compensated system. They are:

This leads to the following pole and zero locations:

Note that the damping ratios of the dominant poles in our compensated systems satisfy the approximate relationship $\zeta \approx \frac{\PM}{100}$ that we derived in the previous section, since our compensated systems have $\PM\approx 49\degree$.

We can compare the step responses of each system as well:

• All designs have zero steady-state error, since our plant was type-1 to begin with.

• The lead design is faster and more damped than the original system, since we have increased the bandwidth and phase margin.

• The lag design is slower and more damped than the original system, since we have decreased the bandwidth and increased the phase margin.

• Both compensated systems have a similar overshoot, which is consistent with their similar damping ratios. However, the overshoot observed is slightly higher than what we would expect from $\zeta\approx 0.49 \implies M_p\approx 17\%$, due to the presence of zeros influencing the dominant pole behavior (see Eq. (26)).

As a final comparison, let’s add some high-frequency noise and see how the different designs perform. We will add sensor noise ($n$ in the block diagram of Figure 1) at frequencies above 100 rad/s, with an amplitude of roughly 1.^[2] This is a lot of noise, given that our step input also has a height of 1; it is for illustrative purposes!

The lead design has a large amount of noise in the response, whereas the lag design has a much cleaner response. We can explain this using the Bode plots:

• As we saw in the previous section, at high frequencies, we have $|T(j\omega)| \approx |L(j\omega)|$. So the open-loop Bode plots give us a good indication of how much noise will be amplified at high frequencies.

• The lead design (see Figure 8) has a magnitude of about -20 dB at 100 rad/s, which means that it attenuates noise by a factor of 10. Our noise had an amplitude of 1, so this is quite visible on the plot of the step response.

• The lag design (see Figure 9) has a magnitude of about -50 dB at 100 rad/s, which means that it attenuates noise by a factor of about 300. This is why the noise is barely visible on the plot of the step response.

• The original system (see Figure 7) had a magnitude of about -30 dB at 100 rad/s, which was in between the lead and lag designs.

Summary¶

Test your knowledge¶

Solution to Exercise 1 #

The system is type zero. Achieving a zero steady-state error to a step input but finite error to a ramp input means that we need to add one integrator. Let’s start with

$$C_1(s) = \frac{k}{s}$$

(28)

The steady state error to a ramp is:

$$\begin{aligned} e_{ss} &= \lim_{s\to 0} s \cdot \frac{1}{1 + C_1(s)G(s)} \cdot \frac{1}{s^2}\\ &= \lim_{s\to 0} \frac{1}{s} \cdot \frac{1}{1 + \frac{k}{s}G(s)} \\ &= \lim_{s\to 0} \frac{1}{s} \cdot \frac{s}{s + k G(s)} \\ &= \frac{1}{k G(0)} = \frac{15}{120 k} \end{aligned}$$

(29)

Since we want the error to be less than 0.05, we need $k > \frac{15}{120 \cdot 0.05} = 2.5$. Let’s pick $k = 3$ to be safe. This gives us the following compensated system:

$$C_1(s)G(s) = \frac{84s + 360}{s(s^2 + 7s + 15)}$$

(30)

Let’s verify that we have achieved our first two design goals by looking at the step and ramp responses of the closed-loop system $\frac{C_1(s)G(s)}{1 + C_1(s)G(s)}$:

We satisfy the first two design goals, but our settling time and percent overshoot are too large. Let’s make the bode plot of $C_1(s)G(s)$:

• We desire a percent overshoot of at most 10%. Using the results in the section on phase margin and damping, this corresponds to $\zeta \approx 0.6$ and a phase margin of about 60°.

• We desire a settling time of at most 0.6 seconds, which we can estimate using the results from the section on bandwidth and settling time. We have $\omega_b \approx \frac{4}{\zeta t_s} \approx \frac{4}{0.6\cdot 0.6} \approx 11$. So we need a bandwidth of at least 11 rad/s.

Therefore, our design goals are to achieve:

$$\boxed{\omega_b \geq 11 \text{ rad/s},\qquad \PM \geq 60\degree}$$

(31)

while maintaining the same steady-state tracking performance. This means leaving the low-frequency loop gain unchanged. The phase margin is about 18°, and the bandwidth is about 9 rad/s. Both need to increase, so a natural candidate is a lead compensator.

We should add 42° of phase lead to get to our target of 60°, and we should add a little extra to account for the gain bump. Let’s pick $\phi_{\textsf{des}} = 50\degree$. Using Eq. (6), we can calculate $\alpha$:

$$\alpha = \frac{1-\sin 50\degree}{1+\sin 50\degree} \approx 0.13$$

(32)

This corresponds to a gain bump of $20\log_{10} \frac{1}{\sqrt{\alpha}} \approx 9$ dB. The uncompensated magnitude plot drops to -9 dB at roughly 15 rad/s, so we will set $\omega_{cg}' = 15$ rad/s. This is convenient because it satisfies the bandwidth spec of at least 11 rad/s!

Next, we pick $\tau$ to correspond to the gain crossover frequency of the uncompensated system, using Eq. (12). This leads us to:

$$\tau = \frac{1}{\omega_{cg}'\sqrt{\alpha}} \approx 0.18$$

(33)

So our lead compensator is:

$$C_2(s) = \frac{\tau s + 1}{\alpha \tau s + 1} = \frac{0.18 s + 1}{0.023 s + 1}$$

(34)

Here is the new Bode plot with the lead compensator:

The phase margin is now about 61° and the bandwidth is about 15 rad/s, so we have achieved our design goals! Let’s double check that our percent overshoot and settling times meet the specifications by looking at the compensated closed-loop step response:

Everything looks good! After including the lead compensation, the percent overshoot is now 10% and the settling time is 0.4 seconds. Our final compensator is the product of the lead compensator and the integrator we designed at the beginning:

$$C(s) = C_1(s)C_2(s) = \frac{3}{s} \cdot \frac{0.18 s + 1}{0.023 s + 1}$$

(35)